The present disclosure relates generally to a semiconductor device and method of forming a semiconductor device on a substrate.
Semiconductor device geometries continue to dramatically decrease in size. Today's fabrication processes are routinely producing devices having feature dimensions less than 65 nm. However, solving the problems associated with implementing new process and equipment technology while continuing to satisfy device requirements has become more challenging. For example, metal-oxide-semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon has advantageous thermal resistive properties and can allow for formation of self aligned source/drain structures. In order to continually meet performance requirements, there has been a desire to replace some of the polysilicon gate electrodes of an integrated circuit with metal gate electrodes. One process of implementing metal gates is termed a “gate last” or “replacement gate” methodology. In such a process, a dummy (e.g., sacrificial) polysilicon gate is initially formed, various processes associated with the semiconductor device are performed, and the dummy gate is subsequently removed and replaced with a metal gate.
The replacement gate process includes one or more chemical mechanical planarization (CMP) processes that can cause gate-height uniformity issues. This, in turn, may cause variation in the semiconductor device (e.g., resistor) performance. Thus, though the present methods and devices are in many ways sufficient and effective for their purposes, it is desired to improve the processes and resultant devices.